Shrinking transistors

Print edition : April 05, 2013

Diagram of a 3D nano-transistor showing the gate (red) surrounding the vertical nanowires (green) and separating the contacts at the ends of each nanowire (beige). Photo: © X-L Han and G. Larrieu

A NEW breakthrough could push the limits of the miniaturisation of electronic components further than previously thought possible. A team at the Laboratoire d’Analyse et d’Architecture des Systemes (LAA), Toulouse, and Institut d’Electronique, de Microelectronique et de Nanotechnologie (IEMN) has built a nanometric transistor that displays exceptional properties for a device of its size.

To achieve this result, the researchers developed a novel three-dimensional architecture consisting of a vertical nanowire array whose conductivity is controlled by a gate measuring only 14 nm in length compared with 28 nm for the transistors in today’s chips. Published in Nanoscale, these findings offer alternatives to the planar structures used in microprocessors and memory units. The use of 3D transistors could significantly increase the power of microelectronic devices.

The “building blocks” of microelectronics, transistors consist of a semiconductor component, called channel, linking two terminals. The flow of current between these terminals is controlled by a third terminal, called gate. Acting like a switch, the gate determines whether the transistor is on or off.

It is now generally agreed that today’s transistors, with their planar architecture, are nearing the limits of miniaturisation: there is a minimum size under which the gate control over the channel becomes less and less effective. In particular, leakage currents begin to interfere with the logical operations performed by the transistor array.

The team has now built the first truly three-dimensional nanometric transistor. The device consists of a tight vertical nanowire array of about 200 nm in length linking two conductive surfaces. A chromium gate completely surrounds each nanowire and controls the flow of current, resulting in optimum transistor control for a system of this size.

This architecture could lead to the development of microprocessors in which the transistors are stacked together. The number of transistors in a given space could thus be increased considerably, along with the performance capacity of microprocessors and memory units. Another significant advantage of these components is that they are relatively simple to manufacture and do not require high-resolution lithography. In addition, these 3D transistors could be easily integrated into the conventional microelectronic devices used by the industry today.

The researchers believe that the size of the gate could be made smaller than 10 nm while still providing satisfactory control over the transistor.

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